This invention relates generally to instruction set computing. In particular the invention relates to a method of executing an instruction set, and an execution processor for executing the instruction set.
Reduced instruction set computing (RISC) processors typically have a fixed bit-width instruction size. Common sizes are 16-bits and 32-bits. 32-bits give flexibility in expressing instructions and operands but at the expense of typically larger code size than the 16-bit instruction sets.
A problem with the short (16-bit) instruction sets is that they have a restricted number of bits for expressing operators. Some processors (for example those operating the reduced instruction set computer architecture MIPS) make use of prefixes. A prefix is an instruction which is associated with another instruction. A prefix contains the same number of bits as the instruction with which it is associated. For example, the MIPS architecture uses short instructions each having 16 bits. Both an MIPS prefix and the MIPS instruction with which it is associated have 16 bits.
Prefixes have been used to signify that a field in an instruction is to be interpreted as having the same meaning but in a different location in the instruction. In a simplified example, FIG. 1a illustrates an instruction in which field A is in location 1, field B is in location 2, field C is in location 3, and field D is in location 4 of an instruction. FIG. 1b illustrates a prefix which precedes the instruction of FIG. 1a and indicates that the fields in locations 1 and 3 of the instruction are to be interchanged. FIG. 1c illustrates the interpretation that the executing processor is left with of the instruction of FIG. 1a as a result of the prefix of FIG. 1b. The operands in locations 1 and 3 have been interchanged. Now field C is in location 1, field B in location 2, field A in location 3, and field D in location 4. This example is a simplified illustration. In a real situation the prefix would be used to carry out other functions as well as indicating that the operands in locations 1 and 3 of the instruction are to be interchanged.
The example of FIGS. 1a, 1b and 1c illustrates a change in the relative location of operators within the instruction. However, short 16-bit instructions are limited compared to long 32-bit instructions in that the number of operators available for use in the short instructions is significantly reduced compared to the number of operators available for use in the long instructions due to the length of the instructions. The method illustrated in FIGS. 1a, 1b and 1c does not increase the number of operators available for use in a short instruction.
There is therefore a need for a method of executing a reduced instruction set which increases the number of operators available for use in the instruction.